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The authors evaluate the performance of variable- versus fixed-size memory pools in tests implementing the two approaches for LTE and WiMAX protocol stacks

The authors describe a variable pool memory management scheme that has been implemented for LTE and WiMAX protocol stacks and has exhibited excellent performance, especially when compared to traditional fixed-pool implementations.

Despite claims that the 8-bit MCU will soon be obsolete by 32-bit devices, that may not exactly be the case.

Lauro Rizzatti at EVE-USA explains why the "Battleship Game" reminds him of trying to debug a system-on-chip (SoC) design using the in-circuit-emulation (ICE) mode.

Here's a guide from Jack Ganssle on doing software development in a disciplined way to reduce both errors and the time it takes to complete a project. Part 3: The value of postmortems

Here's a simple technique to generate a warning that your C++ code is using dynamic allocation against your wishes.

Here's a guide from Jack Ganssle on doing software development in a disciplined way to reduce both errors and the time it takes to complete a project. Part 2: The Seven Step Plan.

Here's a guide from Jack Ganssle on doing software development in a disciplined way to reduce both errors and the time it takes to complete a project. Part 1: Any idiot can write code.

High-temperature semiconductor technologies can survive temperatures approaching 400°C, but careful design of the product is required to deliver cost-effective devices achieving stable, predictable performance.

Deming is dead. Both literally and figuratively.

Understand the key specifications and parameters which are key an effective and reliable capacitive touch screen interface

Some basic tests will verify your PCB/IC thermal modeling and reality

At UBM TechInsights we are often tasked with proving patent infringement of a software algorithm as part of our IP Management Services. Our example algorithm is based on the ARM architecture.

Low-power analog, mixed-signal, and RF building blocks are needed to transform the power-grid plans into reality

This article describes the processing bottlenecks of current microcontroller architectures and explore how to achieve higher processing efficiency by offloading the CPU via coprocessors, accelerating memory access using multi-channel DMA, and eliminating high-speed peripheral and I/O bottlenecks through an integrated event management system.

To be part of the emerging smart power utility grid revolution, you need to get the basics. Here is the lowdown on the design requirements of current basic utility meter apps and how they will evolve to meet future energy needs.

What are the new growth drivers--or next big things--in semiconductors?

Joe Rash of CebaTech argues for protocol acceleration solutions, which leverage the capabilities afforded by FPGAs, to help customers get to market fast and capture market opportunities.